Field of the Invention
The present invention relates to a pattern generation method, a recording medium, an information processing apparatus, and mask fabrication method.
Description of the Related Art
In recent years, as circuit patterns are miniaturized, transfer of a desired pattern on a substrate using a semiconductor exposure apparatus becomes difficult. To address this situation, two methods have been proposed.
First, a technique referred to as a one-dimensional layout technique has been proposed (refer to Michael C. Smayling et. al., “Low k1 Logic Design using Gridded Design Rules” Proc. of SPIE Vol. 6925 p. 69250B (2008)). FIGS. 1A to 1C are diagrams illustrating the one-dimensional layout technique. In the one-dimensional layout technique, a line/space pattern (hereinafter referred to as an “L and S pattern”) illustrated in FIG. 1A is formed in advance and portions of line patterns are removed so that a circuit pattern is fabricated. Specifically, the line patterns are cut using a pattern illustrated in FIG. 1B so that a circuit pattern illustrated in FIG. 1C is obtained. The pattern illustrated in FIG. 1B is referred to as a “cut pattern”. A technique of fabricating a circuit pattern by partially inserting dot patterns in portions of spaces in an L and S pattern is also included in the one-dimensional layout technique. Accordingly, the one-dimensional layout technique is a process performed by transferring a plurality of pattern elements on an L and S pattern formed on a substrate. Use of this technique more easily enables low-k1 when compared with complicated patterns in the related art.
Second, a method for performing exposure by adding assist patterns to a mask pattern has been proposed. The assist patterns are also referred to as SRAFs (Sub-Resolution Assist Features). By using the assist patterns, a larger lithography margin (a degree of freedom of exposure) may be obtained. As a method for positioning assist patterns when a mask pattern including the assist patterns is generated by a computer, Japanese Patent Laid-Open No. 2008-040470 discloses a method using a two-dimensional transmission cross coefficient map. In this method, a two-dimensional TCC (Transmission Cross Coefficient) is calculated using an effective light source and a pupil function, an approximate aerial image map is obtained using the two-dimensional TCC and a mask pattern, and assist patterns are positioned in peak positions of the approximate aerial image map.
In this method, since the assist patterns are positioned in portions for increasing contrast of an image to be transferred, the positions of the assist patterns are determined such that a lithography margin is improved.
Patterns in an entire mask include a single or a plurality of patterns corresponding to a region of a single semiconductor chip. The pattern corresponding to a region of a single semiconductor chip is configured by a combination of circuit pattern groups including a block cell which is a set of functional blocks, an IO unit performing input/output of data, and a standard cell in a logical element unit.
U.S. Pat. No. 7,873,929 discloses an example in which an optical proximity effect generated when a mask pattern is generated by arranging a plurality of standard cells is suppressed by arranging assist patterns around the standard cells in a rule base.
When the method disclosed in Japanese patent Laid-Open No. 2008-040470 is employed in the pattern corresponding to a region of a semiconductor chip having an area of several mm square in order to improve a lithography margin of the region of the semiconductor chip, there arises a situation in that a long period of time is required for calculation for determining arrangement of the assist patterns. For example, a region in which positions of assist patterns may be determined by a single two-dimensional TCC map is approximately several μm square, and therefore, in a region of a semiconductor chip, calculation is performed on as many as several million calculation regions. As a result, a long period of time is required for the calculation for determining the arrangement of assist patterns in the region of a semiconductor chip.
In U.S. Pat. No. 7,873,929, patterns in the standard cells for arranging assist patterns two-dimensionally extend in vertical and horizontal directions, and assist patterns for a pattern used in the one-dimensional layout technique are not generated. Furthermore, assist patterns are generated on the basis of a rule in which the assist patterns are disposed around the cells so as to suppress the light proximity effect from other cells in a chip region in which the cells are arranged. Therefore, it is not necessarily the case that resolving performance of the patterns in the cells is improved.